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| (R) EL5111, EL5211, EL5411 Data Sheet January 10, 2007 FN7119.5 60MHz Rail-to-Rail Input-Output Op Amps The EL5111, EL5211, and EL5411 are low power, high voltage rail-to-rail input-output amplifiers. The EL5111 represents a single amplifier, the EL5211 contains two amplifiers, and the EL5411 contains four amplifiers. Operating on supplies ranging from 5V to 15V, while consuming only 2.5mA per amplifier, the EL5111, EL5211, and EL5411 have a bandwidth of 60MHz (-3dB). They also provide common mode input ability beyond the supply rails, as well as rail-to-rail output capability. This enables these amplifiers to offer maximum dynamic range at any supply voltage. The EL5111, EL5211, and EL5411 also feature fast slewing and settling times, as well as a high output drive capability of 65mA (sink and source). These features make these amplifiers ideal for high speed filtering and signal conditioning application. Other applications include battery power, portable devices, and anywhere low power consumption is important. The EL5111 is available in 5 Ld TSOT and 8 Ld HMSOP packages. The EL5211 is available in the 8 Ld HMSOP package. The EL5411 is available in space-saving 14 Ld HTSSOP packages. All feature a standard operational amplifier pinout. These amplifiers operate over a temperature range of -40C to +85C. Features * Pb-free plus anneal available (RoHS compliant) * 60MHz -3dB bandwidth * Supply voltage = 4.5V to 16.5V * Low supply current (per amplifier) = 2.5mA * High slew rate = 75V/s * Unity-gain stable * Beyond the rails input capability * Rail-to-rail output swing * 180mA output short current Applications * TFT-LCD panels * VCOM amplifiers * Drivers for A-to-D converters * Data acquisition * Video processing * Audio processing * Active filters * Test equipment * Battery-powered applications * Portable equipment Pinouts EL5111 (8 LD HMSOP) TOP VIEW NC 1 VIN- 2 VIN+ 3 VS- 4 + 8 NC 7 VS+ 6 VOUT 5 NC VOUT 1 VS- 2 VIN+ 3 EL5111 (5 LD TSOT) TOP VIEW 5 VS+ VOUTA 1 VINA- 2 4 VINVINA+ 3 VS- 4 EL5211 (8 LD HMSOP) TOP VIEW 8 VS+ + + 7 VOUTB 6 VINB5 VINB+ EL5411 (14 LD HTSSOP) TOP VIEW VOUTA 1 VINA- 2 VINA+ 3 VS+ 4 VINB+ 5 VINB- 6 VOUTB 7 + + + + 14 VOUTD 13 VIND12 VIND+ 11 VS10 VINC+ 9 VINC8 VOUTC +- 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5111, EL5211, EL5411 Ordering Information PART NUMBER EL5111IWT-T7 EL5111IWT-T7A EL5111IWTZ-T7 (Note) EL5111IWTZ-T7A (Note) EL5111IYE EL5111IYE-T7 EL5111IYE-T13 EL5111IYEZ (Note) EL5111IYEZ-T7 (Note) EL5111IYEZ-T13 (Note) EL5211IYE EL5211IYE-T7 EL5211IYE-T13 EL5211IYEZ (Note) EL5211IYEZ-T7 (Note) EL5211IYEZ-T13 (Note) EL5211AIYEZ (Note) EL5211AIYEZ-T7 (Note) EL5211AIYEZ-T13 (Note) EL5411IRE EL5411IRE-T7 EL5411IRE-T13 EL5411IREZ (Note) EL5411IREZ-T7 (Note) EL5411IREZ-T13 (Note) EL5411IR EL5411IR-T7 EL5411IR-T13 EL5411IRZ (Note) EL5411IRZ-T7 (Note) EL5411IRZ-T13 (Note) PART MARKING 8 8 BAAG BAAG 7 7 7 BAAJA BAAJA BAAJA 9 9 9 BAATA BAATA BAATA BBLAA BBLAA BBLAA 5411IRE 5411IRE 5411IRE 5411IREZ 5411IREZ 5411IREZ 5411IR 5411IR 5411IR 5411IRZ 5411IRZ 5411IRZ TAPE & REEL 7" (3k pcs) 7" (250 pcs) 7" (3k pcs) 7" (250 pcs) 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" PACKAGE 5 Ld TSOT 5 Ld TSOT 5 Ld TSOT (Pb-free) 5 Ld TSOT (Pb-free) 8 Ld HMSOP 8 Ld HMSOP 8 Ld HMSOP 8 Ld HMSOP (Pb-free) 8 Ld HMSOP (Pb-free) 8 Ld HMSOP (Pb-free) 8 Ld HMSOP 8 Ld HMSOP 8 Ld HMSOP 8 Ld HMSOP (Pb-free) 8 Ld HMSOP (Pb-free) 8 Ld HMSOP (Pb-free) 8 Ld HMSOP (Pb-free) 8 Ld HMSOP (Pb-free) 8 Ld HMSOP (Pb-free) 14 Ld HTSSOP 14 Ld HTSSOP 14 Ld HTSSOP 14 Ld HTSSOP (Pb-free) 14 Ld HTSSOP (Pb-free) 14 Ld HTSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP (Pb-free) 14 Ld TSSOP (Pb-free) PKG. DWG. # MDP0049 MDP0049 MDP0049 MDP0049 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0050 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0044 MDP0044 MDP0044 M14.173 M14.173 M14.173 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Absolute Maximum Ratings (TA = +25C) Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 65mA Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMIR CMRR AVOL VS+ = +5V, VS- = -5V, RL = 1k to 0V, TA = +25C, Unless Otherwise Specified CONDITIONS MIN TYP MAX UNIT DESCRIPTION Input Offset Voltage Average Offset Voltage Drift (Note 1) Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain VCM = 0V 3 7 15 mV V/C VCM = 0V 2 1 2 -5.5 60 nA G pF +5.5 70 70 V dB dB for VIN from -5.5V to 5.5V -4.5V VOUT 4.5V 50 62 OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short-Circuit Current Output Current IL = -5mA IL = 5mA 4.85 -4.92 4.92 180 65 -4.85 V V mA mA POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current VS is moved from 2.25V to 7.75V No load (EL5111) No load (EL5211) No load (EL5411) DYNAMIC PERFORMANCE SR tS BW GBWP PM CS dG dP NOTES: 1. Measured over operating temperature range. 2. Slew rate is measured on rising and falling edges. 3. NTSC signal generator used. Slew Rate (Note 2) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation Differential Gain (Note 3) Differential Phase (Note 3) f = 5MHz (EL5211 and EL5411 only) RF = RG = 1k and VOUT = 1.4V RF = RG = 1k and VOUT = 1.4V -4.0V VOUT 4.0V, 20% to 80% (AV = +1), VO = 2V step 75 80 60 32 50 110 0.17 0.24 V/s ns MHz MHz dB % 60 80 2.5 5 10 4.5 7.5 15 dB mA mA mA 3 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Electrical Specifications PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMIR CMRR AVOL Input Offset Voltage Average Offset Voltage Drift (Note 4) Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain for VIN from -0.5V to 5.5V 0.5V VOUT 4.5V -0.5 45 62 66 70 VCM = 2.5V VCM = 2.5V 3 7 2 1 2 +5.5 60 15 mV V/C nA G pF V dB dB VS+ = +5V, VS- = 0V, RL = 1k to 2.5V, TA = +25C, Unless Otherwise Specified CONDITION MIN TYP MAX UNIT DESCRIPTION OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short-circuit Current Output Current IL = -5mA IL = 5mA 4.85 80 4.92 180 65 150 mV V mA mA POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current VS is moved from 4.5V to 15.5V No load (EL5111) No load (EL5211) No load (EL5411) DYNAMIC PERFORMANCE SR tS BW GBWP PM CS dG dP NOTES: 4. Measured over operating temperature range. 5. Slew rate is measured on rising and falling edges. 6. NTSC signal generator used. Slew Rate (Note 5) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation Differential Gain (Note 6) Differential Phase (Note 6) f = 5MHz (EL5211 and EL5411 only) RF = RG = 1k and VOUT = 1.4V RF = RG = 1k and VOUT = 1.4V 1V VOUT 4V, 20% to 80% (AV = +1), VO = 2V step 75 80 60 32 50 110 0.17 0.24 V/s ns MHz MHz dB % 60 80 2.5 5 10 4.5 7.5 15 dB mA mA mA 4 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Electrical Specifications PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMIR CMRR AVOL Input Offset Voltage Average Offset Voltage Drift (Note 7) Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain for VIN from -0.5V to 15.5V 0.5V VOUT 14.5V -0.5 53 62 72 70 VCM = 7.5V VCM = 7.5V 3 7 2 1 2 +15.5 60 15 mV V/C nA G pF V dB dB VS+ = +15V, VS- = 0V, RL = 1k to 7.5V, TA = +25C, Unless Otherwise Specified CONDITION MIN TYP MAX UNIT DESCRIPTION OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short-circuit Current Output Current IL = -5mA IL = 5mA 14.85 80 14.92 180 65 150 mV V mA mA POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current VS is moved from 4.5V to 15.5V No load (EL5111) No load (EL5211) No load (EL5411) DYNAMIC PERFORMANCE SR tS BW GBWP PM CS dG dP NOTES: 7. Measured over operating temperature range 8. Slew rate is measured on rising and falling edges 9. NTSC signal generator used Slew Rate (Note 8) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation Differential Gain (Note 9) Differential Phase (Note 9) f = 5MHz (EL5211 and EL5411 only) RF = RG = 1k and VOUT = 1.4V RF = RG = 1k and VOUT = 1.4V 1V VOUT 14V, 20% to 80% (AV = +1), VO = 2V step 75 80 60 32 50 110 0.16 0.22 V/s ns MHz MHz dB % 60 80 2.5 5 10 4.5 7.5 15 dB mA mA mA 5 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Typical Performance Curves 500 QUANTITY (AMPLIFIERS) QUANTITY (AMPLIFIERS) VS=5V TA=+25C 400 300 200 100 0 -12 -10 -8 -6 -4 -2 -0 10 12 2 4 6 8 TYPICAL PRODUCTION DISTRIBUTION 25 VS=5V 20 15 10 5 0 1 3 5 7 9 11 13 15 17 19 21 150 150 TYPICAL PRODUCTION DISTRIBUTION INPUT OFFSET VOLTAGE (mV) INPUT OFFSET VOLTAGE DRIFT, TCVOS (V/C) FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. INPUT OFFSET VOLTAGE DRIFT 2.0 INPUT OFFSET VOLTAGE (mV) INPUT BIAS CURRENT (A) 1.5 1.0 0.5 0.0 -0.5 -50 0.008 VS=5V 0.004 0.000 -0.004 -0.008 -0.012 -50 -10 30 70 110 150 -10 30 70 110 TEMPERATURE (C) TEMPERATURE (C) FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE 4.96 OUTPUT HIGH VOLTAGE (V) OUTPUT LOW VOLTAGE (V) VS=5V IOUT=5mA 4.94 4.92 4.90 4.88 -4.85 VS=5V IOUT=5mA -4.87 -4.89 -4.91 -4.93 -4.95 -50 4.86 -50 -10 30 70 110 150 -10 30 70 110 TEMPERATURE (C) TEMPERATURE (C) FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE 6 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Typical Performance Curves (Continued) 75 VS=5V RL=1k OPEN-LOOP GAIN (dB) 70 SLEW RATE (V/s) 78 VS=5V 77 76 75 74 73 60 -50 72 -50 65 -10 30 70 110 150 -10 30 70 110 150 TEMPERATURE (C) TEMPERATURE (C) FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE 2.9 TA=+25C SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 2.7 2.5 2.3 2.1 1.9 1.7 1.5 4 8 12 16 20 2.70 VS=5V 2.65 2.60 2.55 2.50 2.45 2.40 -50 -10 30 70 110 150 SUPPLY VOLTAGE (V) TEMPERATURE (C) FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE 0.00 DIFFERENTIAL PHASE () 100 IRE 200 -0.02 DIFFERENTIAL GAIN (%) -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -0.18 0 VS=5V AV=2 RL=1k 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 100 IRE 200 FIGURE 11. DIFFERENTIAL GAIN FIGURE 12. DIFFERENTIAL PHASE 7 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Typical Performance Curves (Continued) -30 -40 DISTORTION (dB) -50 -60 2nd HD -70 -80 -90 0 2 4 6 8 10 3rd HD VS=5V AV=2 RL=1k FREQ=1MHz GAIN (dB) 80 60 GAIN 40 20 0 -20 1k PHASE 130 70 10 -50 100M PHASE () 250 190 10k 100k 1M 10M VOP-P (V) FREQUENCY (Hz) FIGURE 13. HARMONIC DISTORTION vs VOP-P FIGURE 14. OPEN LOOP GAIN AND PHASE MAGNITUDE (NORMALIZED) (dB) 3 1 -1 -3 VS=5V AV=1 CLOAD=0pF MAGNITUDE (NORMALIZED) (dB) 5 25 15 5 -5 -15 VS=5V AV=1 RL=1k 1M 10M 100M 1000pF 100pF 47pF 10pF 1k 560 150 -5 100k 1M 10M 100M -25 100k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS RL FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS CL OUTPUT IMPEDANCE () 350 300 250 200 150 100 50 0 10k 100k 1M FREQUENCY (Hz) 10M 100M MAXIMUM OUTPUT SWING (VP-P) 400 12 10 8 6 4 2 VS=5V AV=1 RL=1k DISTORTION <1% 100k 1M FREQUENCY (kHz) 10M 100M 0 10k FIGURE 17. CLOSED LOOP OUTPUT IMPEDANCE FIGURE 18. MAXIMUM OUTPUT SWING vs FREQUENCY 8 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Typical Performance Curves (Continued) -15 -25 CMRR (dB) -35 -45 -55 -65 1k PSRR (dB) -80 PSRR+ -60 PSRR- -40 -20 VS=5V TA=+25C 10k 100k 1M 10M 100M 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 19. CMRR FIGURE 20. PSRR 1K VOLTAGE NOISE (nV/Hz) -60 DUAL MEASURED CH A TO B QUAD MEASURED CH A TO D OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION -80 XTALK (dB) 100 -100 -120 VS=5V RL=1k AV=1 VIN=110mVRMS 10k 100k 1M 10M 30M 10 -140 1 100 1k 10k 100k 1M 10M 100M -160 1k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 21. INPUT VOLTAGE NOISE SPECTRAL DENSITY FIGURE 22. CHANNEL SEPARATION 100 VS=5V AV=1 RL=1k VIN=50mV TA=+25C 5 4 3 STEP SIZE (V) 2 1 0 -1 -2 -3 -4 -5 55 0.1% VS=5V AV=1 RL=1k 80 OVERSHOOT (%) 0.1% 60 40 20 0 10 100 LOAD CAPACITANCE (pF) 1k 65 75 85 95 105 SETTLING TIME (ns) FIGURE 23. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE FIGURE 24. SETTLING TIME vs STEP SIZE 9 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Typical Performance Curves (Continued) VS=5V TA=+25C AV=1 RL=1k VS=5V TA=+25C AV=1 RL=1k 100mV STEP 1V STEP 50ns/DIV 50ns/DIV FIGURE 25. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 26. SMALL SIGNAL TRANSIENT RESPONSE Pin Descriptions EL5111 (TSOT-5) 1 EL5111 (HMSOP8) 6 EL5211 (HMSOP8) 1 EL5411 ( HTSSOP14) 1 NAME VOUTA FUNCTION Amplifier A output EQUIVALENT CIRCUIT VS+ GND VS- CIRCUIT 1 4 2 2 2 VINAAmplifier A inverting input VS+ VS- CIRCUIT 2 3 5 3 7 3 8 5 6 7 3 4 5 6 7 8 9 10 2 4 4 11 12 13 14 1, 5, 8 VINA+ VS+ VINB+ VINBVOUTB VOUTC VINCVINC+ VSVIND+ VINDVOUTD NC Amplifier A non-inverting input Positive power supply Amplifier B non-inverting input Amplifier B inverting input Amplifier B output Amplifier C output Amplifier C inverting input Amplifier C non-inverting input Negative power supply Amplifier D non-inverting input Amplifier D inverting input Amplifier D output Not connected (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 2) 10 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Applications Information Product Description The EL5111, EL5211, and EL5411 voltage feedback amplifiers are fabricated using a high voltage CMOS process. They exhibit rail-to-rail input and output capability, are unity gain stable and have low power consumption (2.5mA per amplifier). These features make the EL5111, EL5211, and EL5411 ideal for a wide range of generalpurpose applications. Connected in voltage follower mode and driving a load of 1k, the EL5111, EL5211, and EL5411 have a -3dB bandwidth of 60MHz while maintaining a 75V/s slew rate. The EL5111 is a single amplifier, the EL5211 a dual amplifier, and the EL5411 a quad amplifier. Short Circuit Current Limit The EL5111, EL5211, and EL5411 will limit the short circuit current to 180mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds 65mA. This limit is set by the design of the internal metal interconnects. Output Phase Reversal The EL5111, EL5211, and EL5411 are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 28 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. VS = 2.5V, TA = +25C, AV = 1, VIN = 6VP-P 1V 10s Operating Voltage, Input, and Output The EL5111, EL5211, and EL5411 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5111, EL5211, and EL5411 specifications are stable over both the full supply range and operating temperatures of -40C to +85C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The input common-mode voltage range of the EL5111, EL5211, and EL5411 extends 500mV beyond the supply rails. The output swings of the EL5111, EL5211, and EL5411 typically extend to within 100mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 27 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from 5V supply with a 1k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.8VP-P. VS = 5V, TA = +25C, AV = 1, VIN = 10VP-P 5V 10s 1V FIGURE 28. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the EL5111, EL5211, and EL5411 amplifiers, it is possible to exceed the +125C 'absolute-maximum junction temperature' under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX - T AMAX P DMAX = ------------------------------------------- JA 5V OUTPUT INPUT (EQ. 1) FIGURE 27. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package 11 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ] 3.5 POWER DISSIPATION (W) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 (EQ. 2) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 2.632W HTSSOP14 JA=+38C/W when sourcing, and: P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ] (EQ. 3) when sinking, where: * i = 1 to 2 for dual and 1 to 4 for quad * VS = Total supply voltage * ISMAX = Maximum supply current per amplifier * VOUTi = Maximum output voltage of the application * ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figures 2936 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves shown in Figures 29-36. JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 0.8 POWER DISSIPATION (W) 694mW 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 85 100 125 HTSSOP14 JA=+144C/W 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 TSSOP28 POWER DISSIPATION (W) 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 1.042W 977mW 893mW 845mW 758mW JA=+120C/W TSSOP24 JA=+128C/W TSSOP20 JA=+140C/W TSSOP16 JA=+148C/W TSSOP14 JA=+165C/W 75 85 100 125 150 AMBIENT TEMPERATURE (C) FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.8 POWER DISSIPATION (W) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 1.667W 1.471W 1.389W 1.289W 1.250W TSSOP28 JA=+75C/W TSSOP24 JA=+85C/W TSSOP20 JA=+90C/W TSSOP16 JA=+97C/W TSSOP14 JA=+100C/W 75 85 100 125 150 AMBIENT TEMPERATURE (C) FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE AMBIENT TEMPERATURE (C) FIGURE 32. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 12 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY (SINGLE LAYER) TEST BOARD 0.350 POWER DISSIPATION (W) POWER DISSIPATION (W) 0.300 0.250 0.200 0.150 0.100 0.050 0.000 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) 150 290mW TSOT5 JA=+345C/W 0.6 0.5 483mW 0.4 0.3 0.2 0.1 0.0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) 150 TSOT5 JA=+207C/W JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.6 POWER DISSIPATION (W) 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) POWER DISSIPATION (W) 486mW HM =+ JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) JA = 870mW HM SO P +1 15 8 C /W JA 20 P8 6 C/ W SO FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 36. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Unused Amplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. Power Supply Bypassing and Printed Circuit Board Layout The EL5111, EL5211, and EL5411 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1F ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7F tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. 13 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D N (N/2)+1 A MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE A PIN #1 I.D. 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00 Max 0.05 0.05 +0.05/-0.06 +0.05/-0.06 0.10 Basic 0.10 Basic 0.15 Reference Rev. E 12/02 A1 A2 b c D E E1 e L H E E1 0.20 C B A 1 B TOP VIEW (N/2) 2X N/2 LEAD TIPS C SEATING PLANE e 0.05 L1 NOTES: b 0.10 C N LEADS SIDE VIEW 0.10 M C A B 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. SEE DETAIL "X" c END VIEW L1 A A2 GAUGE PLANE 0.25 A1 DETAIL X L 0 - 8 14 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 HTSSOP (Heat-Sink TSSOP) Family 0.25 M C A B D N (N/2)+1 A MDP0048 HTSSOP (Heat-Sink TSSOP) Family SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE A PIN #1 I.D. 1.20 0.075 0.90 0.25 0.15 5.00 3.2 6.40 4.40 3.0 0.65 0.60 1.00 14 1.20 0.075 0.90 0.25 0.15 6.50 4.2 6.40 4.40 3.0 0.65 0.60 1.00 20 1.20 0.075 0.90 0.25 0.15 7.80 4.3 6.40 4.40 3.0 0.65 0.60 1.00 24 1.20 0.075 0.90 0.25 0.15 9.70 5.0 6.40 4.40 3.0 0.65 0.60 1.00 28 1.20 0.075 0.90 0.22 0.15 9.70 7.25 6.40 4.40 3.0 0.50 0.60 1.00 38 Max 0.075 +0.15/-0.10 +0.05/-0.06 +0.05/-0.06 0.10 Reference Basic 0.10 Reference Basic 0.15 Reference Reference Rev. 2 12/03 A1 A2 b c E E1 0.20 C B A 1 B TOP VIEW (N/2) 2X N/2 LEAD TIPS D D1 E E1 E2 e L EXPOSED THERMAL PAD D1 E2 L1 N NOTES: BOTTOM VIEW 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 0.05 H C SEATING PLANE e 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. b 0.10 C N LEADS SIDE VIEW 0.10 M C A B SEE DETAIL "X" END VIEW c L1 A A2 GAUGE PLANE 0.25 A1 L 0 - 8 DETAIL X 15 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 TSOT Package Family e1 A N 6 4 MDP0049 D TSOT PACKAGE FAMILY SYMBOL A A1 A2 TSOT5 1.00 0.05 0.87 0.38 0.127 2.90 2.80 1.60 0.95 1.90 0.40 0.60 0.20 5 TSOT6 1.00 0.05 0.87 0.38 0.127 2.90 2.80 1.60 0.95 1.90 0.40 0.60 0.20 6 TSOT8 1.00 0.05 0.87 0.29 0.127 2.90 2.80 1.60 0.65 1.95 0.40 0.60 0.13 8 TOLERANCE Max 0.05 0.03 0.07 +0.07/-0.007 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. A 12/02 NOTES: E1 2 3 E b c D 0.15 C D 2X 5 e B b NX ddd M 1 2 (N/2) 0.25 C 2X N/2 TIPS C A-B D E E1 e e1 L L1 ddd N 0.15 C A-B 2X C D 1 3 A2 SEATING PLANE 0.10 C NX A1 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.15mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (TSOT6 AND TSOT8 only). (L1) H 6. TSOT5 version has no center lead (shown as a dashed line). A GAUGE PLANE c L 4 4 0.25 16 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 HMSOP (Heat-Sink MSOP) Package Family E B 1 E1 N D (N/2)+1 0.25 M C A B MDP0050 HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY SYMBOL A A1 A2 b HMSOP8 HMSOP10 1.00 0.075 0.86 0.30 0.15 3.00 1.85 4.90 3.00 1.73 0.65 0.55 0.95 8 1.00 0.075 0.86 0.20 0.15 3.00 1.85 4.90 3.00 1.73 0.50 0.55 0.95 10 TOLERANCE Max. +0.025/-0.050 0.09 +0.07/-0.08 0.05 0.10 Reference 0.15 0.10 Reference Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. 0 10/03 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". (N/2) PIN #1 I.D. TOP VIEW A c D D1 E EXPOSED THERMAL PAD E2 E1 E2 e D1 L L1 N BOTTOM VIEW e C SEATING PLANE 0.10 C N LEADS b SIDE VIEW H 0.08 M C A B 4. Dimensioning and tolerancing per ASME Y14.5M-1994. L1 A c END VIEW SEE DETAIL "X" A2 GAUGE 0.25 PLANE L 3 3 DETAIL X A1 17 FN7119.5 January 10, 2007 EL5111, EL5211, EL5411 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06 e b 0.10(0.004) M C AM BS A1 0.10(0.004) A2 c E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN7119.5 January 10, 2007 |
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